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VHDL_electronic_organ
- 简易电子琴,可以弹奏音乐。本课程设计主要内容是基于VHDL语言并利用数控分频器设计硬件电子琴,利用GW48作为课程开发硬件平台,键1至键8设计为电子琴键。某一个LED显示当前的按键的音节数。-Simple organ, can play music. The main contents of this curriculum design is based on the VHDL language and the use of digital hardware design divider org
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
fenpinq
- VHDL分频器的设计,可以产生奇数和偶数次分频-VHDL Divider
shepinreliao
- 此为基于FPGA的射频热疗系统的设计,包括温度测量模块,指定温度设计模块,模糊控制器模块,温度显示及分频模块等。-This FPGA-based design of radiofrequency hyperthermia system, including the temperature measurement module, the design of modules specified temperature, the fuzzy controller module, temperature
encoder
- 此为介绍一光电编码器的学术论文,采用VHDL语言编写,介绍了4分频的实现。-This is the descr iption of the papers of a photoelectric encoder using VHDL language, introduced a 4-band implementation.
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
rs232
- fpga的串口读写程序,经硬件测试成功,波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
clk_vhdl
- Quartus II工程压缩文件,是一个典型的基于FPGA的数字钟工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
rs232_VHDL
- RS232 uart的VHDL实现,包括时钟分频(波特率产生),接收,发送-Implement of RS232 uart in VHDL
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
jtdvhdl
- 自己做的VHDL交通灯控制器;分频器、信号控制器、时钟模块;EDA; 通过了仿真、运行。时间可以设置为随意的两位数.-code and jpf
chengxu
- 一个分频器,一个卷积编码器的程序,都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
DCM
- Xilinx公司诸多型号开发版中的一个模块,能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
Fredevider_n
- 任意N偶数倍频率分频器VHDL语言,编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
vhdl-examples
- VHDL写的100多个经典例子,适合初学者。包括分频器,简易时钟等-VHDL written more than 100 classic example, suitable for beginners. Divider, the simple clock
CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时钟频率比外部时钟更高,时钟延迟和时钟偏移最小,减小或调整时钟
1
- 根据交通灯控制器的功能与要求,将其总体电路分为分频器、信号控制器两个模块。-According to the traffic light controller functions and the requirements of the overall circuit is divided into its divider, the signal controller two modules.
VHDL
- 1 8位加法器的设计 2 分频电路 3 数字秒表的设计-1 8 adder design of 2-circuit design of 3 digital stopwatch